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Datasheet File OCR Text:

September 2009
TLE5012 TLE5012-E0318 TLE5012-E0742
GMR-Based Angular Sensor for Rotor Position Sensing
Target
Data Sheet
V 0.46
Sensors
Edition 2009-09 Published by Infineon Technologies AG 81726 Munchen, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
TLE5012
TLE5012 GMR-Based Angular Sensor Revision History: 2009-09, V 0.46 Previous Version: V0.41 Page 13 17 22 27 28 31-46 47 52 Subjects (major changes since last revision) PRO-SIL Disclaimer added Table 2, Magnetic Field Induction and Storage Temperature amended Table 8, Angle Delay Time with Prediction added, Figure 12 updated Table 13, Lock updated; more detailed description of CMD word Table 14, STAT updated Registertype updated Table 16 notes amended Chapter 3.6 addded
general
Correction of typing errors
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com
Target Data Sheet
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V 0.46, 2009-09
TLE5012
1 1.1 1.2 1.3 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.5.1 3.5.1.1 3.5.1.2 3.5.1.3 3.5.1.3.1 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.7 3.7.1 3.7.2 3.7.3 3.7.4 4 4.1 4.2 4.3 4.4 4.5
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 7 8 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SD-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Digital Signal Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Communication (SSC) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE5012 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 17 17 19 19 19 20 21 21 23 24 24 25 27 30 31 46 48 50 52 52 53 53 53 53 54 55 55 55 56 56 56
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Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32
Sensitive Bridges of the GMR Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ideal Output of the GMR Sensor Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TLE5012 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PRO-SILTM Logo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application Circuit for TLE5012 with SSC and PWM Interface (using internal CLK) . . . . . . . . . . . 14 Application Circuit for TLE5012 with HS Mode (using internal CLK) . . . . . . . . . . . . . . . . . . . . . . . 15 Application Circuit for TLE5012 with SSC and IIF Interface (using external CLK) . . . . . . . . . . . . . 15 Application Circuit for TLE5012 with only PWM Interface (using internal CLK) . . . . . . . . . . . . . . . 16 Offset and Amplitude Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TLE5012 Signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Delay of Sensor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 External CLK Timing Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SSC Configuration in Sensor-Slave Mode with Push-Pull Outputs (High Speed Application) . . . . 24 SSC Configuration in Sensor-Slave Mode and Open Drain (Safe Bus Systems) . . . . . . . . . . . . . 25 SSC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SSC Data Transfer (Data Read Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SSC Data Transfer (Data Write Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SSC Bit Ordering (Read Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fast CRC Polynomial Division Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Typical Example for a PWM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HS Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Incremental Interface Protocol with symbolically illustration of SPI-Interface. . . . . . . . . . . . . . . . . 51 IIF Index Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 OV Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PG-DSO-8 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Footprint PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAD Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Push-Pull Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Open Drain Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Command Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Safety Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 17 17 19 19 20 21 22 23 24 25 26 27 28 30 47 48 51 53 55
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V 0.46, 2009-09
TLE5012
1
1.1
Product Description
Overview
The TLE5012 is a 360 angle sensor that detects the orientation of a magnetic field. This is achieved by measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR) elements. High precision angle values are achieved over temperature and lifetime using internal autocalibration algorithm. Data communications are accomplished with a bi-directional SSC Interface that is SPI compatible. The absolute angle value and other values are transmitted via SSC or via a Pulse-Width-Modulation (PWM) Protocol. Also the sine and cosine raw values can be read out. These raw signals are digitally processed internally to calculate the angle orientation of the magnetic field (magnet). The TLE5012 is a precalibrated sensor. The calibration parameters are stored in laser fuses. At start-up the values of the fuses are written into Flip-Flops, where these values can be changed by the application specific parameters. The TLE5012-E0318 and TLE5012-E0742 are especially configured in a Hall-Switch emulation mode for motors with three or seven pole pairs. Online diagnostic functions are provided to ensure reliable operation.
Product Type TLE5012 TLE5012-E0318 TLE5012-E0742 Target Data Sheet
Marking 5012 5012E03 5012E07 7
Ordering Code SP000477068 SP000611246 SP000611250
Package PG-DSO-8 PG-DSO-8 PG-DSO-8 V 0.46, 2009-09
TLE5012
Product Description
1.2
* * * * * * * * * * * * * *
Features
Giant Magneto Resistance (GMR)-based principle Integrated magnetic field sensing for angle measurement Full calibrated 0 - 360 angle measurement with revolution counter and angle speed measurement Two separate highly accurate single bit SD-ADC 15 bit representation of absolute angle value on the output (resolution of 0.01) 16 bit representation of sine / cosine values on the interface Max. 1.0 angle error over lifetime and temperature with activated auto-calibration Bi-directional SSC Interface up to 8Mbit/s Supports SIL3 with diagnostic functions and status information Interfaces: SSC, PWM, Incremental Interface (IIF), Hall Switch Mode (HSM) 0.25 m CMOS technology Automotive qualified: -40C to 150C (Junction Temperature) ESD > 2kV (HBM) Green package with lead-free (Pb-free) plating
1.3
Application Example
The TLE5012 GMR-Based Angular Sensor is designed for angular position sensing in automotive applications, such as: * * * * Electrical Commutated Motor (e.g. used in Electric Power Steering (EPS)) Rotary Switch Steering Angle General Angular Sensing
Target Data Sheet
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V 0.46, 2009-09
TLE5012
Functional Description
2
2.1
Functional Description
General
The GMR sensor is implemented using vertical integration. This means that the GMR sensitive areas are integrated above the logic portion of the TLE5012 device. These GMR elements change their resistance depending on the direction of the magnetic field. Four individual GMR elements are connected to one Wheatstone Sensor Bridge. These GMR elements sense one of two components of the applied magnetic field: * * X component, Vx (cosine) or the Y component, Vy (sine)
The advantage of a full-bridge structure is that the amplitude of the GMR signal is doubled and temperature effects cancel out each other.
GMR Resistors
90
S
0
VX
VY
N
ADCX +
ADCX -
GND
ADCY+
ADCY-
VDD
Figure 1
Sensitive Bridges of the GMR Sensor
Note: In Figure 1, the arrows in the resistors symbolize the direction of the Reference Layer, which is used for the further explanation. The output signal of each bridge is only unambiguous over 180 between two maxima. Therefore two bridges are orientated orthogonally to each other to measure 360. With the trigonometric function ARCTAN, the true 360 angle value can be calulated which is represented by the relation of X and Y signals. Because only the relative values influence the result, the absolute size of the two signals is of minor importance. Therefore, most influences to the amplitudes are compensated.
Target Data Sheet
9
V 0.46, 2009-09
TLE5012
Functional Description
Y Component (SIN)
VY VX V VX (COS)
X Component (COS)
0
90
180
270
360
Angle
VY (SIN)
Figure 2 Ideal Output of the GMR Sensor Bridges
Target Data Sheet
10
V 0.46, 2009-09
TLE5012
Functional Description
2.2
Pin Configuration
8
7
6
5
Center of Sensitive Area
1
Figure 3
2
3
4
Pin Configuration (Top View)
2.3
Pin Description
Table 1 Pin No. 1
Pin Description Symbol CLK In/Out I Function External Clock (must be connected to GND for PWM output) SSC Clock SSC Chip Select SSC Data / IIF Index / Hall Switch Signal 3 Interface A: IIF Phase A; Hall Switch Signal 1 or PWM output (depends on external application circuit) Supply Voltage Ground Interface B: IIF Phase B or Hall Switch Signal 2
2 3 4 5
SCK CSQ DATA / HS3 IFA (IIF_A / HS1 / PWM)
I I I/O O
6 7 8
VDD GND IFB (IIF_B / HS2)
O
Target Data Sheet
11
V 0.46, 2009-09
TLE5012
Functional Description
2.4
Block Diagram
TLE5012
Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Y GMR SDADC SDADC CCU Cordic Fuses Incremental IF PWM HSM SSC Interface
VDD
CLK CSQ SCK
DATA
Temp
IFA IFB GND
Figure 4
TLE5012 Block Diagram
2.5
Functional Block Description
2.5.1
* * *
Internal Power Supply
The internal stages of the TLE5012 are supplied with different voltage regulators. GMR Voltage Regulator VRG Analog Voltage Regulator VRA Digital Voltage Regulator VRD (derived from VRA)
These regulators are directly connected to the supply voltage VDD.
2.5.2
Oscillator and PLL
The internal frequency oscillator feeds the Phase Locked Loop (PLL). Also the external clock (CLK) can be used therefore.
2.5.3
SD-ADC
The SD-ADCs transform the analog GMR-voltages and temperature-voltage into the digital domain.
Target Data Sheet
12
V 0.46, 2009-09
TLE5012
Functional Description
2.5.4
* * *
Digital Signal Processing Unit
The Digital Signal Processing Unit (DSPU) contains the: Capture Compare Unit (CCU), which is used to generate the PWM signal COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle calculation Fuses, which contain the calibration parameters
2.5.5
* * * *
Interfaces
Different Interfaces can be selected: SSC Interface PWM Incremental Interface Hall Switch Mode
2.5.6
Safety Features
The TLE5012 offers a multiplicity on safety features to support Safety Integrity Level (SIL). Sensors with this performance are identified by the following logo:
Figure 5 * * * * * *
PRO-SILTM Logo
Safety features are: Test vectors switchable to ADC- input Inversion or combination of filter input streams Data transmission check via 8bit Cyclic Redundancy Check (CRC) Self test routines Two independent active interfaces possible Overvoltage and undervoltage detection
Disclaimer PRO-SILTM is a Registered Trademark of Infineon Technologies AG. The PRO-SILTM Trademark designates Infineon products which contain SIL Supporting Features. SIL Supporting Features are intended to support the overall System Design to reach the desired SIL (according to IEC61508) or A-SIL (according to ISO26262) level for the Safety System with high efficiency. SIL respectively A-SIL certification for such a System has to be reached on system level by the System Responsible at an accredited Certification Authority. SIL stands for Safety Integrity Level (according to IEC 61508) A-SIL stands for Automotive-Safety Integrity Level (according to ISO 26262)
Target Data Sheet
13
V 0.46, 2009-09
TLE5012
Specification
3
3.1
Specification
Application Circuit
The application circuit in Figure 6, Figure 7, Figure 8 and Figure 9 show the different communication possibilities of TLE5012.
TLE5012
100n Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Y GMR SDADC SDADC CCU Cordic Temp Fuses Incremental IF PWM HSM IFA (PWM) 10 k PWM IFB could be remain open or connected via 10 k resistor to GND. SSC Interface CSQ CLK 1 k
VDD (4.5 - 5.5V)
SCK *)
SSC
DATA
IFB
GND * recommended , e.g. 470
Figure 6
Application Circuit for TLE5012 with SSC and PWM Interface (using internal CLK)
Figure 6 shows a basic block-diagram of the TLE5012 with PWM- Interface. This interface is selectable by connecting CLK to GND. Additionally to the PWM the SSC Interface could be used. Within the SSC- Interface the PWM mode is selectable between Push-Pull and Open Drain.
Target Data Sheet
14
V 0.46, 2009-09
TLE5012
Specification
TLE5012
Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Y GMR SDADC SDADC CCU Cordic Temp Fuses Incremental IF PWM HSM IFA (HS1) SSC Interface CSQ CLK *) *) *) 100n
VDD (4.5 - 5.5V)
SCK
DATA (HS3)
IFB (HS2) GND
* recommended , e.g. 2.2 k
Figure 7
Application Circuit for TLE5012 with HS Mode (using internal CLK)
Figure 7 shows a basic block-diagram of the TLE5012 with HS Mode. This interface is selectable by connecting CLK to GND and CSQ to VDD. Additionally to the HSM the SSC Interface could be used by pulling CSQ to GND. Within the SSC- Interface the HS Mode is selectable between Push-Pull and Open Drain.
TLE5012
Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Y GMR SDADC SDADC CCU Cordic Temp Fuses Incremental IF PWM HSM IFA (IIF_A) CCU SSC Interface CSQ CLK
VDD (4.5 - 5.5V)
100n **) ***) PLL
C
SCK *) SSC
DATA
IFB (IIF_B)
GND *) recommended , e.g. 470 **) connected to V DD for use of internal CLK ***) connected to microcontroller for use of external CLK
Figure 8
Application Circuit for TLE5012 with SSC and IIF Interface (using external CLK)
Figure 8 shows a basic block-diagram of an angle sensor system using a TLE5012 and a microcontroller for rotor positioning applications. The depicted Interface-Configuration is needed for High-Speed applications like electrical commutated motor drives. It is possible to connect the TLE5012 to a microcontroller via Incremental Interface and for safety reasons also via SSC-Interface. Target Data Sheet 15 V 0.46, 2009-09
TLE5012
Specification
TLE5012
Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Y GMR SDADC SD ADC CCU Cordic Temp Fuses Incremental IF PWM HSM IFA (PWM) 10 k SSC Interface CSQ CLK 100 n 1 k
VDD (4.5 - 5.5V)
SCK 10 k
DATA
DATA and IFB could be remain open or connected via 10 k resistor to GND .
IFB
GND
Figure 9
Application Circuit for TLE5012 with only PWM Interface (using internal CLK)
Target Data Sheet
16
V 0.46, 2009-09
TLE5012
Specification
3.2
Absolute Maximum Ratings
Table 2 Parameter
Absolute Maximum Ratings Symbol Min. VDD VIN TJ B -0.5 -0.5 -40 Values Typ. Max. 6.5 6.5 150 150 125 100 70 60 150 V V C C mT mT mT mT C for 1000h not additive max. 5 min @ tA = 25C max. 5 h @ tA = 25C max. 1000h @ tA = 85C; not additive max. 1000h @ tA = 100C; not additive without magnetic field max 40 h/Lifetime additionally VDD + 0.5 V may not be exceeded Unit Note / Test Condition
Voltage on VDD pin respect to ground (VSS) Voltage on any pin respect to ground (VSS) Junction Temperature Magnetic Field Induction
Storage Temperature
TST
-40
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the device.
3.3
Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 3 is valid for -40C < TJ < 150C. Table 3 Parameter Supply Voltage Output Current (DATA-Pad) Operating Range Symbol Min. VDD IQ 4.5 Output Current (IFA / IFB-Pad) Input Voltage IQ VIN -0.3 Values Typ. 5.0 Max. 5.5 -25 -5 -0.4 -15 -5 5.5 V mA mA mA mA mA V
1)
Unit Note / Test Condition
PAD_DRV ='0x', sink current2) PAD_DRV ='10', sink current2) PAD_DRV ='11', sink current2) PAD_DRV ='0x', sink current2) PAD_DRV ='1x', sink current2) VDD + 0.3 V may not be exceeded
Target Data Sheet
17
V 0.46, 2009-09
TLE5012
Specification Table 3 Parameter Magnetic Induction Angle Range Operating Range (cont'd) Symbol Min. BXY Ang 30 0 Values Typ. Max. 50 360 mT in X/Y direction3) Unit Note / Test Condition
1) Directly blocked with 100nF ceramic capacitor 2) Max. current to GND over Open Drain Output 3) Values refer to an homogenous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT).
Note: The thermal resistances listed in Table 20 "Package Parameters" on Page 55 must be used to calculate the corresponding ambient temperature. Calculation of the Junction Temperature The total power dissipation PTOT of the chip increases its temperature above the ambient temperature. The power multiplied by the total thermal resistance RthJA (Junction to Ambient) leads to the final junction temperature. RthJA is the sum of the addition of the values of the two components Junction to Case and Case to Ambient.
RthJA = RthJC + RthCA TJ = TA + T T = RthJA x PTOT = RthJA x (VDD x I DD + VOUT x I OUT )
Example (assuming no load on Vout):
(1)
(IDD, I OUT > 0, if direction is into IC)
VDD = 5V I DD = 12mA K T = 150 x 5[V ]x 0.012[A] + 0[VA] = 9 K W
For moulded sensors, the calculation with RthJC is more adequate.
(2)
Target Data Sheet
18
V 0.46, 2009-09
TLE5012
Specification
3.4
Characteristics
3.4.1
Electrical Parameters
The indicated electrical parameters apply to the full operating range, unless otherwise specified. The typical values correspond to a supply voltage VDD = 5.0 V and 25 C, unless individually specified. All other values correspond to -40 C < TJ < 150C. Table 4 Parameter Supply Current POR Level POR Hysteresis Power On Time Input Signal Low Level Input Signal High Level Pull-Up Current Pull-Down Current Output Signal Low Level Electrical Parameters Symbol Min. IDD VPOR VPORhy tPon VL VH IPU IPD VOL 2.0 -10 -10 10 10 Values Typ. 12 30 4 Max. 13 2.9 5 0.3 VDD -225 -150 225 150 1 mA V mV ms V V A A A A V CSQ DATA SCK CLK, IFA, IFB DATA; IQ = - 25 mA (PAD_DRV='0x'), IQ = - 5 mA (PAD_DRV='10'), IQ = - 0.4 mA (PAD_DRV='11') IFA,IFB; IQ = - 15 mA (PAD_DRV='0x'), IQ = - 5 mA (PAD_DRV='1x') VDD > VDDmin1) Power On Reset Unit Note / Test Condition
0.7 VDD -
-
-
1
V
1) Within "Power On Time" write access is not permitted
3.4.2
ESD Protection
Table 5 Parameter
ESD Protection Symbol VHBM VSDM Values min. max. 2.0 0.5 kV kV Human Body Model1) Socketed Device Model2) Unit Notes
ESD Voltage
1) Human Body Model (HBM) according to: JEDEC EIA/JESD22-A114-B 2) Socketed Device Model (SDM) according to: ESD ASS.STD.DS5.3-93
Target Data Sheet
19
V 0.46, 2009-09
TLE5012
Specification
3.4.3
GMR Parameters
All parameters apply over the full operating range, unless otherwise specified. Table 6 Parameter X, Y output range X, Y amplitude
1)
Basic GMR Parameters Symbol Min. RGADC AX, AY k OX, OY X 0, Y0 6000 3922 87.5 9500 100 Values Typ. Max. 23230 15781 20620 112.49 +2047 +11.24 +5000 digits digits digits % digits digits at calibration conditions operating range at calibration conditions at calibration conditions at calibration conditions without magnet 4) Unit Note / Test Condition
X, Y synchronism 2) X, Y offset
3)
-2048 0 -11.25 0 -5000 -
X, Y orthogonality error X, Y without field
1) 2) 3) 4)
see Figure 10 k = 100*(AX/AY) OY=(YMAX + YMIN) / 2; OX = (XMAX + XMIN) / 2 Not tested
VY
+A
0
Offset 0 90 180 270 360
Angle
-A
Figure 10
Offset and Amplitude Definition
Target Data Sheet
20
V 0.46, 2009-09
TLE5012
Specification
3.4.4
Angle Performance
After internal calculation the sensor has a remaining error, as shown in Table 7. The error value refers to BZ = 0mT and the operating conditions given in Table 3 "Operating Range" on Page 17. The overall angle error represents the relative angle error. This error describes the deviation to the reference line after zero angle definition. Table 7 Parameter Overall Angle Error (with autocalibration) Angle Performance Symbol Min. Err Values Typ. 0.6
1)
Unit
Note / Test Condition including lifetime and temperature drift2)3) including temperature drift2)3)
Max. 1.0 1.6
Overall Angle Error (without auto- Err calibration)
0.61)
1) At 25C, B =30 mT 2) Including hysteresis error, caused by revolution direction change. 3) Only with calibrated GMR-compensation parameters of customer setup; Relative error after zero angle definition.
Autocalibration The autocalibration enables online parameter calculation and reduces therefore the angle error due to misalignments. After start-up the parameters out of the fuses get loaded into flip-flops. The TLE5012 updates these parameters after a full revolution. The update can be chosen within the Autocalibration Mode (AUTOCAL) bit. It is possible to do the update after every 22.5, 11.25 or after tupd.
3.4.5
Signal Processing
The signal path of the TLE5012 is depicted in Figure 11. It consists of the GMR-bridge, ADC, filter and angle calculation. Depending on the filter configuration a different total delay time is achieved. Additional to this delay time, the delay time of the interface has to be considered. The delay time leads to an additional angle error at higher speeds. With enabling the prediction, the signal delay time will be reduced (Figure 12).
TLE5012 Microcontroller
tupd
X GMR SDADC Filter Angle Calculation Y GMR SDADC Filter IF
tdel
Figure 11 TLE5012 Signal path
tdelIF
At FIR_MD = 0 only raw values can be read out, due to the more time consuming angle calculation.
Target Data Sheet
21
V 0.46, 2009-09
TLE5012
Specification
Table 8 Parameter
Signal Processing Symbol Min. tupd Values Typ. 21.3 42.7 85.3 170.6 60 80 120 20 5 -40 0.11 0.08 0.05 0.04 Max. 70 95 140 30 20 -20 s s s s s s s s s s FIR_MD = 0 (only raw values)1)2) FIR_MD = 11)2) FIR_MD = 2 (default)1)2) FIR_MD = 31)2) FIR_MD = 11)2) FIR_MD = 21)2) FIR_MD = 31)2) FIR_MD = 1; PREDICT = 1
1)2)
Unit
Note / Test Condition
Update Rate at Interface
Angle Delay Time3)
tdel
-
Angle Delay Time with Prediction3)
tdel
-
FIR_MD = 2; PREDICT = 1
1)2)
FIR_MD = 3; PREDICT = 1
1)2)
Angle Noise
NAngle
-
FIR_MD = 0, (1 Sigma)2) FIR_MD = 1, (1 Sigma)2) FIR_MD = 2, (1 Sigma)2) (default) FIR_MD = 3, (1 Sigma)2)
1) depends on internal oscillator frequency variation (Chapter 3.4.6) 2) guaranteed by laboratory characterization 3) valid at constant rotation speed
Angle Magnetic field direction
Sensor output With Prediction Without Prediction
tdel
Figure 12 Delay of Sensor Output
tupd
time
Target Data Sheet
22
V 0.46, 2009-09
TLE5012
Specification
3.4.6
Clock Supply (CLK Timing Definition)
If the external clock supply is selected, the clock signal input 'CLK' must fulfill certain requirements which are described in the following: * * * The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width and must be spike filtered. The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min). The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is generated automatically.
tCLK tCLKh tCLKl VH VL t
Figure 13 Table 9 Parameter Input Frequency CLK Duty Cycle CLK Rise Time CLK Fall Time Digital Clock Internal Oscillator Frequency
1)2)
External CLK Timing Definition CLK Timing Specification Symbol Min. fCLK CLKDUTY tCLKr tCLKf fDIG fCLK 3.8 30 22.8 3.8 Values Typ. 4.0 50 24 4.0 Max. 4.2 70 30 30 25.2 4.2 MHz % ns ns MHz MHz from VL to VH from VH to VL Unit Note / Test Condition
1) Minimum Duty Cycle Factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min)= 1 / fCLK(f_min) 2) Maximum Duty Cycle Factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max)= tCLK(f_min) - tCLKl(min)
Target Data Sheet
23
V 0.46, 2009-09
TLE5012
Specification
3.5
Interfaces
Within the register MOD_3, the driver strength and so the slope can be varied of the sensor output. The driver strength is specified in Table 3 and the slope fall and rise time in Table 10. Table 10 Parameter Output Fall Time Output Rise Time PAD Characteristic Symbol Min. tfall, trise Values Typ. Max. 8 28 45 130 10 tbd ns ns ns ns ns ns DATA, 50pF, PAD_DRV='00' DATA, 50pF, PAD_DRV='01' DATA, 50pF, PAD_DRV='10' DATA, 20pF, PAD_DRV='11' IFA/IFB, 20pF, PAD_DRV='0x' IFA/IFB, 20pF, PAD_DRV='1x' Unit Note / Test Condition
3.5.1
Synchronous Serial Communication (SSC) Interface
The 3-pin SSC Interface has a bi-directional push-pull data line, serial clock signal and chip select. The SSC Interface is designed to communicate with a microcontroller peer to peer for fast applications.
SSC Communication for peer to peer Data Transmission between TLE5012 and C
(SSC Slave) TLE 5012
**) MRST
C (SSC Master)
Shift Reg.
EN
DATA
Shift Reg.
EN
MTSR
SCK
*)
SCK
Clock Gen.
CSQ
*)
CSQ
*) optional , e.g. 100 **) optional , e.g. 470
Figure 14
SSC Configuration in Sensor-Slave Mode with Push-Pull Outputs (High Speed Application)
Target Data Sheet
24
V 0.46, 2009-09
TLE5012
Specification Another possibility is a 3-pin SSC Interface with bidirectional open-drain data line, serial clock signal and chip select. This setup is designed to communicate with a microcontroller in a bus system, together with other SSC slaves (e.g. two TLE5012 for redundancy reasons). This mode can be activated using bit SSC_OD.
(SSC Slave) TLE 5012
typ. 1k *) *) MRST
C (SSC Master)
Shift Reg.
DATA
Shift Reg.
MTSR
SCK
*)
SCK
Clock Gen.
CSQ
*)
CSQ
*) optional , e.g. 100
Figure 15
SSC Configuration in Sensor-Slave Mode and Open Drain (Safe Bus Systems)
3.5.1.1
SSC Timing Definition
tCSs
tSCKp
tCSh
tCSoff
CSQ
tSCKh tSCKl
SCK
DATA
tDATAs
tDATAh
Figure 16
SSC Timing
SSC Inactive Time (CSoff) The SSC inactive time defines the delay time after a transfer before the TLE5012 can be selected again. Table 11 Parameter SSC Baud Rate CSQ Setup Time CSQ Hold Time Target Data Sheet SSC Push-Pull Timing Specification Symbol Min. fSSC tCSs tCSh 105 105 Values Typ. 8.0 25 Max. Mbit/s ns ns V 0.46, 2009-09 Unit Note / Test Condition
TLE5012
Specification Table 11 Parameter CSQ off SCK Period SCK High SCK Low DATA Setup Time DATA Hold Time Write Read Delay Table 12 Parameter SSC Baud Rate CSQ Setup Time CSQ Hold Time CSQ off SCK Period SCK High SCK Low DATA Setup Time DATA Hold Time Write Read Delay SSC Push-Pull Timing Specification (cont'd) Symbol Min. tCSoff tSCKp tSCKh tSCKl tDATAs tDATAh twr_delay 600 120 40 30 25 40 130 125 Values Typ. Max. ns ns ns ns ns ns ns SSC inactive time Unit Note / Test Condition
SSC Open Drain Timing Specification Symbol Min. fSSC tCSs tCSh tCSoff tSCKp tSCKh tSCKl tDATAs tDATAh twr_delay 300 400 600 500 25 40 130 Values Typ. 2.0 190 190 Max. Mbit/s ns ns ns ns ns ns ns ns ns SSC inactive time Pull-up Resistor = 1k Unit Note / Test Condition
Target Data Sheet
26
V 0.46, 2009-09
TLE5012
Specification
3.5.1.2
* * *
SSC Data Transfer
The SSC data transfer is word aligned. The following transfer words are possible: Command word (to access and change operating modes of the TLE5012) Data words (any data transferred in any direction) Safety word (confirms the data transfer and provide status information)
twr_delay
COMMAND
READ Data 1
READ Data 2
SAFETY-WORD
SSC-Master is driving DATA SSC-Slave is driving DAT A
Figure 17
SSC Data Transfer (Data Read Example)
twr_delay
COMMAND
WRITE Data 1
SAFETY-WORD
SSC-Master is driving DATA SSC-Slave is driving DAT A
Figure 18
SSC Data Transfer (Data Write Example)
Command Word The TLE5012 is controlled by a command word. It is sent first at every data transmission.The structure of the command word is shown in Table 13, where the UPD-bit allows the access to current values or updated values. If an update command is issued and the update bit (UPD) is set, the immediate values are stored in the update buffer simultaneously. This enables a snapshot of all necessary system parameters at the same time. Bits with an update buffer are marked by an "u" in type of register description. The initialization of such an update is descripted on page 29. Table 13 Name RW Structure of the Command Word Bits [15] Description Read - Write 0:Write 1:Read 4 bit Lock Value 0000B: Default Operating Access for addresses 0x00:0x04 1010B: Config- Access for addresses 0x05:0x11
Lock
[14..11]
Target Data Sheet
27
V 0.46, 2009-09
TLE5012
Specification Table 13 Name UPD Structure of the Command Word Bits [10] Description Update-Register Access 0: Access to current values 1: Access to updated values 6 bit Address 4 bit Number of Data-Words
ADDR ND Safety Word
[9..4] [3..0]
The safety word contains following bits: Table 14 Name STAT Structure of the Safety Word Bits [15] Description Indication of Chip-Reset (resets after readout) via SSC 0: Reset occurred 1: No reset Reset: 1B System Error (e.g. Overvoltage; Undervoltage; VDD-, GND- off; ROM;...) 0: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_ADCM) 1: No error Interface Access Error (access to wrong address; wrong lock) 0: Error occurred 1: No error Valid Angle Value (no system error; no interface error; NO_GMR_A = '0'; NO_GMR_XY='0') 0: Angle value invalid 1: Angle value valid Sensor Number Response Indicator The sensor no. bit is pulled low and the other bits are high. Cyclic Redundancy Check (CRC) Chip and Interface Status
[14]
[13]
[12]
RESP CRC
[11..8] [7..0]
Target Data Sheet
28
V 0.46, 2009-09
TLE5012
Specification Data Communication via SSC
SSC Transfer Command Word SCK DATA CSQ RW LOCK SSC -Master is driving DAT A SSC -Slave is driving DAT A UPD ADDR LENGTH MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB MSB 1 LSB
twr_delay
Data Word (s)
Figure 19 * * * * * * * * * * * *
SSC Bit Ordering (Read Example)
The data communication via SSC interface has the following characteristic: The data transmission order is "Most Significant Bit (MSB) first". Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK. The SSC Interface is word-aligned. All functions are activated after each transmitted word. A "high" condition on the negated Chip Select pin (CSQ) of the selected TLE5012 interrupts the transfer immediately. The CRC calculator is automatically reset. After changing the data direction, a delay (twr_delay) has to be considered before continuing the data transfer. This is necessary for internal register access. Every access to the TLE5012 with the number of data (ND) 1 is performed with address auto-increment. At an overflow at address 3FH the transfer continuous at address 00H. With ND = 0 no auto-increment is done and a continuously readout of the same address can be realized. Afterwards no Safety Word is send and the transfer ends with high condition on CSQ. After every data transfer with ND 1 the 16 bit Safety Word will be appended by the selected TLE5012. At a rising edge of CSQ without data transfer before (no SCK-pulse), the update-registers are updated with according values. After sending the Safety Word the transfer ends. To start another data transfer, the CSQ has to be deselected once for tCSoff. The SSC is default Push-Pull. The Push-Pull driver is only active, if the TLE5012 has to send data, otherwise the Push-Pull is disabled for receiving data from the microcontroller.
Cyclic Redundancy Check (CRC) * * * * * * This CRC is according to the J1850 Bus-Specification. Every new transfer resets the CRC generation. Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)). Generator-Polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used (see Figure 20) The remainder of the fast CRC circuit is initial set to '11111111B'. Remainder is inverted before transmission.
Serial CRC output
X7
1
X6
1
X5
1
X4
1
xor
X3
1
X2 xor
1
X1 xor
1
X0 1
&
xor
Input TX_CRC
parallel Remainder
Figure 20
Fast CRC Polynomial Division Circuit 29 V 0.46, 2009-09
Target Data Sheet
TLE5012
Specification
3.5.1.3
Registers Chapter
This chapter defines the registers of the TLE5012. It also defines the read/write access rights of the specific registers. Table 15 identifies the values with symbols. Access to the registers is accomplished via the SSC Interface.
Table 15
Registers Overview Register Long Name Status Register Activation Status Register Angle Value Register Angle Speed Register Angle Revolution Register Frame Synchronization Register Interface Mode1 Register SIL Register Interface Mode2 Register Interface Mode3 Register Offset X Offset Y Synchronicity IFAB Register Interface Mode4 Register Temperature Coeffizient Register X-raw value Y-raw value Offset Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H Page Number 31 33 34 35 35 36 37 38 39 40 41 42 42 43 44 45 45 46
Register Short Name STAT ACSTAT AVAL ASPD AREV FSYNC MOD_1 SIL MOD_2 MOD_3 OFFX OFFY SYNCH IFAB MOD_4 TCO_Y ADC_X ADC_Y
Registers Chapter, TLE5012 Register
The register is addressed wordwise.
Target Data Sheet
30
V 0.46, 2009-09
TLE5012
Specification
3.5.1.3.1
TLE5012 Register
Status Register
STAT Status Register
Offset 00H
Reset Value 8001H
Field RD_ST
Bits 15
Type r
Description Read Status 0B after readout 1B status values changed Reset: 1B Slave Number is given at startup by the external circuit of IFA and IFB. Reset: 00B No GMR Angle Value 0B valid GMR angle value on the interface 1B no valid GMR angle value on the interface Reset: 0B No GMR XY Values 0B valid GMR_XY values on the interface 1B no valid GMR_XY values on the interface Reset: 0B Status ROM 0B after readout, CRC ok 1B CRC fail or running Reset: 0B Status ADC-Test 0B after readout 1B Test vectors out of limit Reset: 0B
S_NR
14:13
rw
NO_GMR_A
12
ru
NO_GMR_XY
11
ru
S_ROM
10
r
S_ADCT
9
ru
Target Data Sheet
31
V 0.46, 2009-09
TLE5012
Specification Field S_MAGOL Bits 7 Type ru Description Status Magnitude Out of Limit 0B after readout 1B GMR-magnitude out of limit (>23230 digits) Reset: 0B Status X,Y Data Out of Limit 0B after readout 1B X,Y data out of limit (>23230 digits) Reset: 0B Status Overflow 0B after readout 1B DSPU overflow occurred Reset: 0B Status Digital Signal Processing Unit 0B after readout 1B DSPU self test not ok, or selftest is running Reset: 0B Status Fuse CRC 0B after readout, Fuse CRC ok 1B Fuse CRC fail Reset: 0B Status Voltage Regulator 0B after readout 1B VDD overvoltage; VDD undervoltage; VDD-off; GNDoff; or VOVG; VOVA; VOVD too high Reset: 0B Status Watchdog 0B after chip reset 1B watchdog counter expired Reset: 0B Status Reset 0B after readout 1B indication of power-up, short power-break or active reset Reset: 1B
S_XYOL
6
ru
S_OV
5
ru
S_DSPU
4
ru
S_FUSE
3
ru
S_VR
2
ru
S_WD
1
ru
S_RST
0
ru
Target Data Sheet
32
V 0.46, 2009-09
TLE5012
Specification Activation Status Register
ACSTAT Activation Status Register
Offset 01H
Reset Value 5EFEH
Field Res AS_ADCT AS_VEC_MAG
Bits 15:10 9 7
Type rw rw rw
Description Reserved Reset: 010111B Enable GMR Vector check Reset: 1B Activation of ADC-Redundancy-BIST 0B after execution 1B activation of redundancy BIST Reset: 1B Activation of ADC-BIST 0B after execution 1B activation of BIST Reset: 1B Enable of DSPU Overflow Check Reset: 1B Activation DSPU BIST 0B after execution 1B activation of DSPU BIST Reset: 1B Activation Fuse CRC 0B after execution 1B activation of Fuse CRC Reset: 1B Enable Voltage Regulator Check Reset: 1B Enable DSPU Watchdog-HW-Reset Reset: 1B
AS_VEC_XY
6
rw
AS_OV AS_DSPU
5 4
rw rw
AS_FUSE
3
rw
AS_VR AS_WD
2 1
rw rw
Target Data Sheet
33
V 0.46, 2009-09
TLE5012
Specification Field AS_RST Bits 0 Type rw Description Activation of Hardware Reset Activation occurs after CSQ switches from '0' to '1' after SSC transfer. 0B after execution 1B activation of HW Reset Reset: 0B
Angle Value Register
AVAL Angle Value Register
Offset 02H
Reset Value 8000H
Field RD_AV
Bits 15
Type r
Description Read Status, Angle Value 0B after readout 1B new angle value (ANG_VAL) present Reset: 1B Calculated Angle Value (ANG_RANGE = 0x080) 4000H -180 0000H 0 3FFFH +179.99 Reset: 0H
ANG_VAL
14:0
ru
Target Data Sheet
34
V 0.46, 2009-09
TLE5012
Specification Angle Speed Register
ASPD Angle Speed Register
Offset 03H
Reset Value 8000H
Field RD_AS
Bits 15
Type r
Description Read Status, Angle Speed 0B after readout 1B new angle speed value (ANG_SPD) present Reset: 1B Calculated Angle Speed Without prediction difference between two consecutive angle values. With prediction, difference between three consecutive angle values. Reset: 0H
ANG_SPD
14:0
ru
Angle Revolution Register
AREV Angle Revolution Register
Offset 04H
Reset Value 8000H
Target Data Sheet
35
V 0.46, 2009-09
TLE5012
Specification
Field RD_REV
Bits 15
Type r
Description Read Status, Revolution 0B after readout 1B new value (REVOL) present Reset: 1B Frame Counter (unsigned 6 bit value) Counts every new angle value Reset: 0H Number of Revolutions (signed 9 bit value) If prediction is enabled, revolution counter is one schedule delayed related to ANG_VAL. Reset: 0H
FCNT
14:9
rwu
REVOL
8:0
ru
Frame Synchronization Register
FSYNC Frame Synchronization Register
Offset 05H
Reset Value 0000H
Field FSYNC
Bits 15:9
Type rwu
Description Frame Synchronization Counter Value Sub counter within one frame. Reset: 0H
Target Data Sheet
36
V 0.46, 2009-09
TLE5012
Specification Interface Mode1 Register
MOD_1 Interface Mode1 Register
Offset 06H
Reset Value 8001H
Field FIR_MD
Bits 15:14
Type rw
Description Filter Decimation Setting 00B 21.3s 01B 42.7s 10B 85.3s 11B 170.6s Reset: 10B Clock Source Select 0B internal oscillator 1B external 4MHz clock Reset: 0B SSC-Interface 0B Push-Pull 1B Open Drain (default within TLE5012-E0318 and TLE5012-E0742) Reset: 0B Hold DSPU Operation 0B DSPU in normal schedule operation 1B DSPU is on hold Reset: 0B Incremental Interface Mode 00B IIF disabled 01B A/B operation with Index on DATA 10B not allowed 11B not allowed Reset: 01B
CLK_SEL
4
rw
SSC_OD
3
rw
DSPU_HOLD
2
rw
IIF_MOD
1:0
rw
Target Data Sheet
37
V 0.46, 2009-09
TLE5012
Specification SIL Register
SIL SIL Register
Offset 07H
Reset Value 0000H
Field FILT_PAR
Bits 15
Type rw
Description Filter Parallel 0B filter parallel disabled 1B filter parallel enabled (source: X-value) Reset: 0B Filter Inverted 0B filter inverted disabled 1B filter inverted enabled Reset: 0B Fuse Reload 0B fuse reload disabled 1B fuse parameters reloaded to DSPU at next cycle start Reset: 0B ADC-Test vectors 0B ADC-Test vectors disabled 1B ADC-Test vectors enabled Reset: 0B Test vector Y 000B 0V 001B +70% 010B +100% 011B +Overflow 101B -70% 110B -100% 111B -Overflow Reset: 0H
FILT_INV
14
rw
FUSE_REL
10
rw
ADCTV_EN
6
rw
ADCTV_Y
5:3
rw
Target Data Sheet
38
V 0.46, 2009-09
TLE5012
Specification Field ADCTV_X Bits 2:0 Type rw Description Test vector X 000B 0V 001B +70% 010B +100% 011B +OV 101B -70% 110B -100% 111B -OV Reset: 0H
Interface Mode2 Register
MOD_2 Interface Mode2 Register
Offset 08H
Reset Value 0800H
Field ANG_RANGE
Bits 14:4
Type rw
Description Angle Range Angle Range [] = 360 * (27 / ANG_RANGE) 200H represents 90 080H represents 360 Reset: 080H Angle Direction 0B counterclockwise rotation of magnet 1B clockwise rotation of magnet Reset: 0B Prediction 0B prediction disabled 1B prediction enabled (default within TLE5012-E0318 and TLE5012-E0742) Reset: 0B
ANG_DIR
3
rw
PREDICT
2
rw
Target Data Sheet
39
V 0.46, 2009-09
TLE5012
Specification Field AUTOCAL Bits 1:0 Type rw Description Autocalibration Mode 00B no autocalibration 01B autocalibration time mode (1LSB parameter change every tupd) (default within TLE5012-E0318 and TLE5012-E0742) 10B autocalibration angle mode1 (1LSB parameter change every 22.5) 11B autocalibration angle mode2 (1LSB parameter change every 11.25) Reset: 00B
Interface Mode3 Register
MOD_3 Interface Mode3 Register
Offset 09H
Reset Value 0000H
Field ANG_BASE
Bits 15:4
Type rw
Description Angle Base 800H -180 000H 0 001H 0.0879 7FFH +179.912 Reset: 000H Analog Spike Filters of Input Pads 0B spike filter disabled 1B spike filter enabled Reset: 0B
SPIKEF
3
rw
Target Data Sheet
40
V 0.46, 2009-09
TLE5012
Specification Field PAD_DRV Bits 1:0 Type rw Description Configuration of Pad-Driver 00B IFA/IFB: strong driver, DATA: strong driver, fast edge 01B IFA/IFB: strong driver, DATA: strong driver, slow edge 10B IFA/IFB: weak driver, DATA: medium driver, fast edge (default within TLE5012-E0318 and TLE5012-E0742) 11B IFA/IFB: weak driver, DATA: weak driver, slow edge Reset: 00B
Offset X Register
OFFX Offset X
Offset 0AH
Reset Value 0000H
Field X_OFFSET
Bits 15:4
Type rw
Description Offset Correction of X-value Reset: 0H
Target Data Sheet
41
V 0.46, 2009-09
TLE5012
Specification Offset Y Register
OFFY Offset Y
Offset 0BH
Reset Value 0000H
Field Y_OFFSET
Bits 15:4
Type rw
Description Offset Correction of Y-value Reset: 0H
Synchronicity Register
SYNCH Synchronicity
Offset 0CH
Reset Value 0000H
Field SYNCH
Bits 15:4
Type rw
Description Amplitude Synchronicity +2047D 112.494% 0D 100% -2048D 87.500% Reset: 0H
Target Data Sheet
42
V 0.46, 2009-09
TLE5012
Specification IFAB Register
IFAB IFAB Register
Offset 0DH
Reset Value 0003H
Field ORTHO
Bits 15:4
Type rw
Description Orthogonality Correction of X and Y Components +2047D 11.2445 0D 0 -2048D -11.2500 Reset: 0H IFA & IFB Open Drain 0B Push-Pull 1B Open Drain (default within TLE5012-E0318 and TLE5012-E0742) Reset: 0B HSM Hysteresis 00B 0 01B 0.09 10B 0.27 11B 0.625 Reset: 11B
IFAB_OD
2
rw
IFAB_HYST
1:0
rw
Target Data Sheet
43
V 0.46, 2009-09
TLE5012
Specification Interface Mode4 Register
MOD_4 Interface Mode4 Register
Offset 0EH
Reset Value 0000H
Field TCO_X_T HSM_PLP
Bits 15:9 7:5
Type rw rw
Description Offset Temperature Coefficient for X-Component Reset: 0H Hall Switch Mode; Polepair Configuration 000B 2 pole pairs 001B 3 pole pairs (default within TLE5012-E0318) 010B 4 pole pairs 011B 6 pole pairs 100B 7 pole pairs (default within TLE5012-E0742) 101B 8 pole pairs 110B 12 pole pairs 111B 16 pole pairs Reset: 000B IFAB Resolution 00B 12bit = 0.088 (244Hz) 01B 11bit = 0.176 (488Hz) 10B 10bit = 0.352 (977Hz) 11B 9bit = 0.703 (1953Hz) Reset: 00B Interface Mode PWM, HSM if CLK is connected to GND at startup. Note: Not mentioned combinations are not allowed 000B SSC mode; IIF 001B SSC mode; PWM 010B SSC mode; HSM (default within TLE5012-E0318 and TLE5012-E0742) Reset: 000B
IFAB_RES
4:3
rw
IF_MD
2:0
rw
Target Data Sheet
44
V 0.46, 2009-09
TLE5012
Specification Temperature Coeffizient Register
TCO_Y Temperature Coeffizient Register
Offset 0FH
Reset Value 0000H
Field TCO_Y_T CRC_PAR
Bits 15:9 7:0
Type rw rw
Description Offset Temperature Coefficient for Y-Component Reset: 0H CRC of Parameters CRC of parameters from address 08H to 0FH Reset: 0H
X-raw Value Register
ADC_X X-raw value
Offset 10H
Reset Value 0000H
Field ADC_X
Bits 15:0
Type r
Description ADC value of X-GMR Read out of this register will update ADC_Y Reset: 0H
Target Data Sheet
45
V 0.46, 2009-09
TLE5012
Specification Y-raw Value Register
ADC_Y Y-raw value
Offset 11H
Reset Value 0000H
Field ADC_Y
Bits 15:0
Type r
Description ADC value of Y-GMR Updated when ADC_X or ADC_Y is read. Reset: 0H
3.5.2
Pulse Width Modulation Interface
The Pulse Width Modulation (PWM) Interface can be selected by connecting CLK to VDD. The PWM update rate can be programmed within the register 0EH (IFAB_RES) in following steps: * * * * 0.25 kHz with 12 bit resolution 0.5 kHz with 11 bit resolution 1.0 kHz with 10 bit resolution (default) 2.0 kHz with 9 bit resolution
PWM uses a square wave with constant frequency whose duty cycle is modulated resulting in an average value of the waveform. Figure 21 shows the principle behavior of a PWM with different duty cycles and the definition of timing values. The duty cycle of a PWM is defined by following general formulas:
Duty Cycle =
ton t PWM
t PWM = t on + toff f PWM = 1 t PWM
(3)
The range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. More details are given in Table 16.
Target Data Sheet
46
V 0.46, 2009-09
TLE5012
Specification
UIFA
Vdd
ON = High level
OFF = Low level
tON
Duty cycle = 5%
tPWM
t OFF
Duty cycle = 50%
UIFA
0'
Vdd
t
UIFA
0'
Vdd
Duty cycle = 95%
t
0'
Figure 21 Table 16 Parameter PWM Output Frequency Output Duty Cycle Range Typical Example for a PWM Signal PWM Interface Symbol Min. fPWM DYPWM 244 6.25 2 98 Values Typ. Max. 1953 93.75 Hz % % % Unit Note / Test Condition
t
selectable by IFAB_RES1) Absolute Angle Electrical Error (S_RST; S_VR) System Error (S_FUSE; S_OV; S_XYOL; S_MAGOL; S_ADCT) Short to GND Short to VDD, Power-Loss
2)
0 99 PWM Period Variation
IFAB_RES
-
1 100 5
% % %
tPWMvar
-5
1) fPWM = (fDIG * 2 ) / (24 * 4096) 2) depends on internal oscillator frequency variation (Chapter 3.4.6)
Target Data Sheet
47
V 0.46, 2009-09
TLE5012
Specification
3.5.3
Hall Switch Mode
The Hall Switch Mode (HSM) within the TLE5012 allows to emulate the output of three Hall switches. Hall switches are often used in electrical commutated motors to get information of the rotor position. With these three output signals the motor will be commutated in the right way. Depending on the used pole pairs of the rotor, different amount of electrical periods have to be realized. This is selectable within 0EH (HSM_PLP). Within the TLE5012E0318 three polepairs and within the TLE5012-E0742 seven polepairs are fused. Figure 22 depicts the three output signals with the relationship between electrical angle and mechanical angle. The mechanical 0 point is always used as reference.
Hall-Switch-Mode: 3phase Generation Electrical Angle 0 60 120 180 240 300 360
HS1
HS2
HS3
Angle
Mech. Angle with 8 Pole Pairs Mech. Angle with 3 Pole Pairs
Figure 22
0 0
7.5 20
15 40
22.5 60
30 80
37.5 100
45 120
Hall Switch Mode
The HSM Interface can be selected by connecting CLK to GND and CSQ has to be logic "1". Table 17 Parameter Rotation Speed Hall Switch Mode Symbol Min. n Values Typ. Max. 10000 rpm Unit Note / Test Condition
Target Data Sheet
48
V 0.46, 2009-09
TLE5012
Specification Table 17 Parameter Electrical Angle Accuracy Hall Switch Mode Symbol Min. elect Mechanical Angle Switching Hysteresis Electrical Angle Switching Hysteresis4) HShystm HShystel 0 Fall Time Rise Time
1) 2) 3) 4)
Values Typ. 1.2 1.8 2.4 3.6 4.2 4.8 7.2 9.6 1.25 1.88 2.50 3.75 4.38 5.00 7.50 10 0.02 0.4 Max. 2 3 4 6 7 8 12 16 0.625 1 1
Unit
Note / Test Condition 2 polepairs with autocalibration1)2) 3 polepairs with autocal.1)2) 4 polepairs with autocal.1)2) 6 polepairs with autocal.1)2) 7 polepairs with autocal.1)2) 8 polepairs with autocal.1)2) 12 polepairs with autocal.1)2) 16 polepairs with autocal.1)2)

selectable by IFAB_HYST3) 2 polepairs; IFAB_HYST=111)2) 3 polepairs; IFAB_HYST=111)2) 4 polepairs; IFAB_HYST=111)2) 6 polepairs; IFAB_HYST=111)2) 7 polepairs; IFAB_HYST=111)2) 8 polepairs; IFAB_HYST=111)2) 12 polepairs; IFAB_HYST=111)2) 16 polepairs; IFAB_HYST=111)2)
tHSfall tHSrise
-
s s
RL = 2.2k; CL < 50pF RL = 2.2k; CL < 50pF
depends on internal oscillator frequency variation (Chapter 3.4.6) guaranteed by design including GMR hysteresis The hysteresis has to be considered only at change of rotation direction.
To avoid switching on mechanical vibrations of the rotor, a hysteresis is recommended (Figure 23).
Target Data Sheet
49
V 0.46, 2009-09
TLE5012
Specification
Ideal Switching Point
HShystel HShystel elect
Figure 23 HS Hysteresis
0
elect
3.5.4
Incremental Interface
The Incremental Interface (IIF) uses an up/down counter of a microcontroller for the angle transmission. The synchronization is done by the parallel active SSC-Interface. The angle value read out by the SSC-Interface can be compared with the stored counter value. In case of a non-synchronization, the microcontroller add the difference to the actual counter value to synchronize the TLE5012 with the microcontroller. The resolution of the IIF can be selected within the interface mode4 register (MOD_4) under IFAB_RES. A/B Mode The phase shift between phase A and B indicates a clockwise (B follows A) or a counterclockwise (A follows B) rotation of the magnet.
Target Data Sheet
50
V 0.46, 2009-09
TLE5012
Specification
VDD CSQ N SSC iGMRSensor INC SCK DATA IFA IFB A B 12bit Up/Down Counter SSC C
S
GND
CSQ SPI Interface SCK DATA D0 D1 D2 D3
D11 D13 D14 D15
90 el. Phase shift Phase A VH VL Incremental Interface Phase B VH VL Counter 0 1 2 3 4 3 2 1
Figure 24
Incremental Interface Protocol with symbolically illustration of SPI-Interface
Index Signal The Index-Signal is generated via Data pin, while CSQ is high (no SSC-communication). The Index-Signal is coded in quadrants via a PWM-sequence, Figure 25.
Angle
0
90
180
270
0
INDEX
t0
Figure 25 Table 18 Parameter Incremental output Frequency IIF Index Coding Incremental Interface Symbol
t 90
t180
t270
Values Min. Typ. Max. 1.0 -
Unit MHz
Note / Test Condition Frequency of Phase A and Phase B
fInc
Target Data Sheet
51
V 0.46, 2009-09
TLE5012
Specification Table 18 Parameter Index Incremental Interface (cont'd) Symbol Min. t0 t90 t180 t270 5 10 15 20 Values Typ. Max. s s s s 0 90 180 270 Unit Note / Test Condition
3.6
Test Structure
3.6.1
ADC Test Vectors
It is possible to feed the ADCs with appropriate values to simulate a certain magnet position and other GMR effects. This test can be activated within SIL register (ADCTV_EN). With ADCTV_Y and ADCTV_X the vector length can be adjusted like Figure 26. The values are generated with resistors on the chip. The following X/Y ADC values can be programmed: * * * * 4 points, circle amplitude = 70% (0,90, 180, 270) 8 points, circle amplitude = 100% (0, 45, 90, 135, 180, 225, 270, 315) 8 points, circle amplitude = 122.1% (35.3, 54.7, 125.3, 144.7, 215.3, 234.7, 305.3, 324.7) 4 points, circle amplitude = 141.4% (45, 135, 225, 315)
ADCTV_Y
122.1% 141.4%
0%
100 .0% 70%
ADCTV_X
Figure 26
ADC Test Vectors
Target Data Sheet
52
V 0.46, 2009-09
TLE5012
Specification
3.7
Overvoltage Comparators
Various comparators monitor the voltage in order to ensure error free operation. The overvoltages must be active at least 256 periods of tDIG to set the test comparator bits in the SSC Interface registers. This works as digital spike suppression. Table 19 Parameter Overvoltage Detection Test Comparators Symbol Min. VOVG VOVA VOVD VDD Overvoltage VDD Undervoltage GND - Off Voltage VDD - Off Voltage Spike Filter Delay VDDOV VDDUV VGNDoff VVDDoff tDEL Values Typ. 2.80 2.80 2.80 6.05 2.70 -0.55 0.55 10 Max. V V V V V V V s Unit Note / Test Condition
3.7.1
Internal Supply Voltage Comparators
Every voltage regulator has an overvoltage comparator to detect a malfunction. If the nominal output voltage of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated.
VDDA REF VDD VRG VRA VRD GND
Figure 27 OV Comparator
+
GND
10s Spike Filter
xxx_OV
3.7.2
VDD Overvoltage Detection
The Overvoltage Detection Comparator monitors the external supply voltage at the VDD pin. It activates the S_VR bit.(Figure 27)
3.7.3
GND - Off Comparator
The GND - Off Comparator is used to detect a voltage difference between the GND pin and SCK. It activates the S_VR bit of the SSC - Interface. This circuit can detect a disconnection of the Supply GND Pin.
Target Data Sheet
53
V 0.46, 2009-09
TLE5012
Specification
VDD
Diodereference
VDDA
SCK
+dV
+
GND
GND
1s Mono Flop
10s Spike Filter
GND_OFF
Figure 28
GND - Off Comparator
3.7.4
VDD - Off Comparator
The VDD - Off Comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLE5012 is supplied by the SCK and CSQ input pins via the ESD structures. It activates the S_VR bit.
VDDA VDD VVDDoff CSQ SCK GND
Figure 29 VDD - Off Comparator
-dV
+
GND
1s Mono Flop
10s Spike Filter
VDD _OFF
Target Data Sheet
54
V 0.46, 2009-09
TLE5012
Package Information
4
4.1
Package Information
Package Parameters
Table 20 Parameter
Package Parameters Symbol Limit Values min. typ. max. RthJA RthJC RthJL 150 200 75 85 MSL 3 Cu Sn 100% > 7 m Unit K/W K/W K/W Notes Junction to Air1) Junction to Case Junction to Lead 260C
Thermal Resistance
Soldering Moisture Level Lead Frame Plating
1) according to Jedec JESD51-7
4.2
Package Outline
1.75 MAX.
0.35 x 45
4 -0.2 1)
+0.06
0.175 0.07 (1.45)
1.27
2) 0.41 +0.1 -0.06
B 0.2
M
0.19
0.1 A B 8x SEATING PLANE
0.64 0.25
E
6 0.2
0.2
8MAX.
M
A
C 1.22 0.18
C 8x
4)
D
8
3 x 1.27 = 3.81
5
Detail A
o0.6 Sensitive Area 3)
Index Marking
1
4
A
0.75 D E CENTER OF SENSITIVE AREA
5 -0.2 1)
1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area 3) Max. 3 tilt of sensitive area to preference "B" 4) Reference "D" is defined with the center of all 8 pins
P-PG-DSO-08-16-S-PO V03
Figure 30
PG-DSO-8 Package Dimension
Target Data Sheet
55
0.32 MIN.
V 0.46, 2009-09
TLE5012
Package Information
4.3
Footprint
1.31
0.65 5.69 1.27
Figure 31
Footprint PG-DSO-8
4.4
Packing
8
0.3
12 0.3
5.2
6.4
1.75 2.1
Figure 32
Tape and Reel
4.5
Marking
Position 1st Line 2nd Line 3rd Line Processing
Marking 5012xx xxx Gxxxx
Description See ordering table on page 7 Lot code G..green, 4-digit..date code
Note: For processing recommendations, please refer to Infineon's Notes on processing
Target Data Sheet
56
V 0.46, 2009-09
www.infineon.com
Published by Infineon Technologies AG

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